For nonvolatile memories, two operations need to be enabled by the design that are changing the storage state of the NVM memory cells, namely erasing and writing. In this regard, erasing is typically possible only for larger chunks of data such as words, blocks, wordlines, or sectors. For that purpose, the larger chunk of stored data is reset by the erase operation to the same default value—for example either “all-0” or “all-1”. In contrast to that, writing is necessarily possible in a bitwise—i.e. selective—way to enable storage of arbitrary data for each memory cell or bit individually.
Bitwise writing can either be an implementation of a highly parallel but nevertheless slow method such as e.g. “Fowler-Nordheim”-tunneling, or a fast but highly power consuming and therefore low parallel method, such as for example “Hot Electron” injection.
For area-efficient flash memories, the erase granularity or selectivity is currently typically at least a wordline (≧1000 Bits), therefore a selective erasure of single words or even single bits is not possible. Conventionally, an erase operation that is capable of selecting individual words typically requires the implementation of an area-inefficient EEPROM array. This implies that “word switches” need to be integrated in the memory array itself that allow to select the corresponding words for individual erasure.
Under certain circumstances, a fast bitwise erase operation may be highly favorable also for flash memories. For instance, this may be the case when single erased cells are disturbed during writing of a different portion of data. In this case, the whole page would have to be erased again and rewritten, resulting in an unexpected effective write time delay of several orders of magnitude.